`define marcos usage in system verilog
时间：2014-02-12 23:58:36
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Note it is not supported in verilog
link from
https://verificationacademy.com/forums/systemverilog/define-macros-usage
1 `define xyz(I,R)\
2 assign abc[I].clk = R.du``I``_clk_x;
2 assign abc[I].clk = R.du``I``_clk_x;
`define xyz(I,R)\
assign abc(I).clk = ``R``.du``I``_clk_x;
assign abc(I).clk = ``R``.du``I``_clk_x;
in the macro, R by itself is the
argument that gets substituted. ``R`` is not needed.
However, the argument I shows up twice in the body of the macro; first by itself, and then surrounded by ``I``. The `` is a token separator used to build identifiers and strings. Without it, the bare argument I would disappear into an identifier duI_clk_x. You want the macro
`xyz(1,a)
to be replaced with
assign abc(1).clk = a.du1_clk_x;
原文：http://www.cnblogs.com/testset/p/3546073.html
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